november 2012 fdmc2523p p-channel qfet ? ?2012 fairchild semiconductor corporation fdmc2523p rev.c3 www.fairchildsemi.com 1 fdmc2523p p-channel qfet ? -150v, -3a, 1.5 features ? max r ds(on) = 1.5 at v gs = -10v, i d = -1.5a ? low crss ( typical 10pf) ? fast switching ? low gate charge ( typical 6.2 nc ) ? improved dv / dt capability ? rohs compliant general description these p-channel mosfet enhancement mode power field effect transistors are produced using fairchild's proprietary, planar stripe, dmos technology. this advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. these devices are well suited for low voltage applications such as audio amplifier, high efficiency sw itching dc/dc converters, and dc motor control. application ? active clamp switch mosfet maximum ratings t a = 25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage -150 v v gs gate to source voltage 30 v i d drain current -continuous t c = 25c -3 a -continuous t c = 100c -1.8 -pulsed -12 p d power dissipation (steady state) t c = 25c 42 w t j , t stg operating and storage junction temperature range -55 to +150 c t l maximum lead temperature for soldering purposes, 1/8? from case for 5 seconds 300 c dv/dt peak diode recovery dv/dt (note 2) -5 v/ns r jc thermal resistance, junction to case (note 1) 3.0 c/w r ja thermal resistance, junction to ambient (note 1a) 60 device marking device package reel size tape width quantity fdmc2523p fdmc2523p mlp 3.3x3.3 13 ?? 12 mm 3000 units bottom d d d d s s s g top pin 1 mlp 3.3x3.3 s s s g d d d d
fdmc2523p p-channel qfet ? fdmc2523p rev.c3 www.fairchildsemi.com 2 electrical characteristics t j = 25c unless otherwise noted symbol parameter test conditions min typ max units off characteristics bv dss drain to source breakdown voltage i d = -250 p a, v gs = 0v -150 v ' bv dss ' t j breakdown voltage temperature coefficient i d = -250 p a, referenced to 25 c -138 mv/ c i dss zero gate voltage drain current v ds = -150v, v gs = 0v -1 p a t j = 125 c -10 i gss gate to source leakage current v gs = 30v, v ds = 0v 100 na on characteristics v gs(th) gate to source threshold voltage v gs = v ds , i d = -250 p a -3 -3.8 -5 v ' v gs(th) ' t j gate to source threshold voltage temperature coefficient i d = -250 p a, referenced to 25 c 6 mv/ c r ds(on) static drain to source on resistance v gs = -10v, i d = -1.5a 1.1 1.5 : v gs = -10v, i d = -1.5a , t j = 125 c 2.0 3.6 g fs forward transconductance v ds = -40v, i d = -1.5a (note 4) 1.4 s dynamic characteristics c iss input capacitance v ds = -25v, v gs = 0v, f = 1mhz 200 270 pf c oss output capacitance 60 80 pf c rss reverse transfer capacitance 10 15 pf r g gate resistance f = 1mhz 7.5 : switching characteristics t d(on) turn-on delay time v dd = -75v, i d = -3a v gs = -10v, r gen = 25 : (note 3,4) 15 27 ns t r rise time 11 20 ns t d(off) turn-off delay time 19 35 ns t f fall time 13 24 ns q g total gate charge v gs = -10v v dd = -75v i d = -3a (note 3,4) 6.2 9 nc q gs gate to source gate charge 1.4 nc q gd gate to drain ?miller? charge 3.3 nc drain-source diod e characteristics i s maximum continuous drain - source diode forward current -3 a i sm maximum pulse drain - source doide forward current -12 a v sd source to drain diode forward voltage v gs = 0v, i s = -3.0a -1.8 -5 v t rr reverse recovery time i f = -3.0a, di/dt = 100a/ p s (note 3) 93 ns q rr reverse recovery charge 0.27 nc notes: 1: r t ja is the sum of the junction-to-case and case-to- ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. r t jc is guaranteed by design while r t ca is determined by the user's board design. 2: i sd < -3a, di/dt < 300a/us, v dd < b vdss , starting t j = 25c 3: pulse test: pulse width < 300 p s, duty cycle < 2.0%. 4: essentially independent of operating temperature. a. 60c/w when mounted on a 1 in 2 p a d o f 2 o z c o p p e r b.135c/w when mounted on a minimum pad of 2 oz copper
fdmc2523p p-channel qfet ? fdmc2523p rev.c3 www.fairchildsemi.com 3 typical characteristics t j = 25c unless otherwise noted figure 1. 0246810 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v gs = -8v v gs = -9v v gs = -6v v gs = -7v v gs = -10v pulse duration = 300 p s duty cycle = 2.0%max -v ds , drain to source voltage (v) - i d , drain current (a) on-region characteristics figure 2. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.8 1.0 1.2 1.4 1.6 v gs = -9v v gs = -8v v gs = -10v v gs = -7v pulse duration = 300 p s duty cycle = 2.0%max v gs = -6v -i d , drain current(a) normalized drain to source on-resistance n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n - r e s i s t a n c e -50 -25 0 25 50 75 100 125 150 0.3 0.6 0.9 1.2 1.5 1.8 2.1 i d = -3a v gs = -10v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 5678910 1.0 1.5 2.0 2.5 3.0 3.5 4.0 pulse duration = 300 p s duty cycle = 2.0%max t j = 125 o c t j = 25 o c i d = -0.75a r ds(on) , drain to source on-resistance ( : ) -v gs , gate to source voltage (v) o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 2345678 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v dd = -5v pulse duration = 300 p s duty cycle = 2.0%max t j = -55 o c t j = 25 o c t j = 125 o c - i d , drain current (a) -v gs , gate to source voltage (v) figure 6. 0.0 0.5 1.0 1.5 2.0 2.5 1e-4 1e-3 0.01 0.1 1 10 t j = -55 o c t j = 25 o c t j = 125 o c v gs = 0v - i s , reverse drain current (a) -v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
fdmc2523p p-channel qfet ? fdmc2523p rev.c3 www.fairchildsemi.com 4 figure 7. 02468 0 2 4 6 8 10 i d = -3a v dd = -75v v dd = -100v v dd = -50v -v gs , gate to source voltage(v) q g , gate charge(nc) gate charge characteristics figure 8. 0 25 50 75 100 125 150 1 10 100 1000 c iss f = 1mhz v gs = 0v capacitance (pf) -v ds , drain to source voltage (v) c rss c oss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 10 -2 10 -1 10 0 10 1 1 6 0.5 20 t j = 125 o c t j = 25 o c i as , avalanche current(a) t av , time in avalanche ( p s ) u n c l a m p e d i n d u c t i v e switching capability figure 10. 11 01 0 0 1e-3 0.01 0.1 1 10 10s 100us 1ms 10ms 100ms 1s dc i d , drain current (a) v ds , drain to source voltage (v) 40 single pulse t j = max rated r t ja = 135 o c/w t a = 25 o c 400 r ds(on) limited f o r w a r d b i a s s a f e operating area figure 11. single pulse maximum power dissipation 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 1 10 100 single pulse r t ja = 135 o c/w 0.5 p ( pk ) , peak transient power (w) t, pulse width (s) 500 t a = 25 o c i = i 25 for temperatures above 25 o c derate peak current as follows: 150 t a ? 125 ----------------------- - typical characteristics t j = 25c unless otherwise noted
fdmc2523p p-channel qfet ? fdmc2523p rev.c3 www.fairchildsemi.com 5 figure 12. transient thermal response curve 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 1e-3 0.01 0.1 1 single pulse r t ja = 135 o c/w d = 0.5 0.2 0.1 0.05 0.02 0.01 duty cycle-descending order t, rectangular pulse duration (s) normalized thermal impedance, z t ja 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a typical characteristics t j = 25c unless otherwise noted
fdmc2523p p-channel qfet ? fdmc2523p rev.c3 www.fairchildsemi.com 6 dimensional outline and pad layout
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